HIGHLIGHTS
- Small form factor (1U, only 40cm deep)
- Supports lossless processing of network data up to 400Gbps at line rate
- Reliable and low latency due to FPGA architecture
- Up to 4x 100G QSFP28 interfaces - or 4x 40G QSFP+ / 8x 25G (fan-out) / 16x10G (fan-out)
- Supports individual configurations for 10G, 25G, 40G, 50G or 100G
- Supports nanosecond timestamping according to IEEE 1588v2 PTP
- Supports export of LiveFlow (IPFIX, NetFlow) data to NPM tools
- Scalable and easy to commission
- Replaceable fans and redundant power supplies
KEY FEATURES
- Line-rate FPGA features/functionalities:
- Advanced Filtering
- Frame length, header length or payload length
- Frame errors
- L2 Protocol/Encapsulation
- L3 IPversion/Protocol/Encapsulation
- L4 Protocol (Ports)/Tunnel
- Pattern compare
- Complex expressions via logical operators (NOT,AND,OR)
- Advanced Deduplication - removal or forwarding of duplicate packets with a programmable deduplication window of 10 µs to 2 seconds. Configurable packet signatures (masking of variable fields e.g. TTL/Hoplimit, DSCP/TraffType, exclusion of Outer Encapsulations, and more).
- Masking (for sensitive information in the packets)
- Slicing/snapping/truncation/trimming - payload removal so that the Ethernet packet contains only the desired number of bytes or information, including a programmable number of bytes offset. Including FCS recalculation. Metadata is preserved. Enables, among other things, to ensure GDPR compliance.
- Decapsulation/Header Stripping/Header Removal - MPLS, VLAN, VNTag, GTP, PPTP, ERSPAN, VxLAN, GRE, GENEVE, LISP, NVGRE, PPPoE, CFP/FabricPath, EoMPLS, IP-in-IP, MAC-in-MAC and custom/user defined encapsulations
- De-tunneling (Tunnel Termination) for traffic generated by vTAPs, ERSPAN,VxLAN
- GTP Filtering
- Timestamping - with nanosecond accuracy is applied to each processed packet using a PTP time server. Locally or via external PTP grandmaster according to IEEE 1588v2.
- High precision PCAP Replay at original rate and at any desired rates
- Source port labeling and VLAN tagging
- Load-balancing on multiple VLAN tags - wide range of hashing algorithms (e.g. 5 tuple, 2 tuple, VLAN, MPLS, customisable, etc).
- Low Latency Aggregation - Consolidation of incoming network traffic to optimise port usage. 1:1 and Many:1
- FPGA accelerated features/functionalities:
- Loopback (shuffling the L2,L3,L4 sources and destinations)
- Entire payload masking
- Host features/functionalities:
- Secure Web GUI
- PCAP viewer
- PCAP composer/editor
HARDWARE
- 1x Intel XEON Scalable
- 2x 10G LAN management por
- Redundant and hot-swappable AC power supplies
- 64GB DDR4 RAM
- NVMe SSD storage for the operating system
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